The present invention relates to a dynamic random access memory (DRAM) of a split word line drive configuration, and particularly to an improvement in the layout of the word line drive circuit
A variety of DRAMs have been proposed one being disclosed in Japanese Patent Application Kokoku Publication 1714/1985. FIG. 1 shows an example employing the folded-bit line configuration and the split word line drive configuration.
The DRAM shown in FIG. 1 comprises first and second memory cell arrays 1-1 and 1-2 disposed on the left and on the right as seen in the figure. Word line drive circuits are disposed in a block 2 between the memory cell arrays 1-1 and 1-2. First and second blocks of sense amplifiers 8-1 and S-2 are disposed on the top sides 1-1c and 1-2c and on the bottom sides 1-1d and 1-2d of the memory cell arrays 1-1 and 1-2.
The word line drive circuits in the block 2 drive the word lines in the first and the second memory cell arrays, and are activated by the output lines 4-1, 4-2 etc. of a row decoder B which decodes a row address ADr.
Because the time taken for the word lines to be fully raised after the corresponding decoder output lines rise determines the access time of the DRAM, it must be short enough. As the degree of integration is increased, however, the number of memory cells connected to each word line is increased, and the word line drive circuit, particularly the transistors therein are required to have a larger capacity. This means that the area each drive transistor must occupy is enlarged. On the other hand, it is also required that the pitch of the word lines be reduced for a higher degree of integration. Thus, to increase the degree of integration two contradictory requirements are encountered: on one hand, larger areas are needed for the drive circuits for a larger driving capacity and, on the other hand, the areas for the drive circuits must be confined in a smaller vertical extension (dimension in the direction orthogonal to the word lines).